Apple has acquired Xnor.ai, a Seattle startup specializing in low-power, edge-based artificial intelligence tools

https://www.geekwire.com/2020/exclusive-apple-acquires-xnor-ai-edge-ai-spin-paul-allens-ai2-price-200m-range/

More about xnor.ai
https://www.embedded-vision.com/what-embedded-vision/embedded-vision-academy/provider/xnor

AI chip-design startup EdgeCortix brings total funding to US$4 Million with extended seed round
https://www.linkedin.com/pulse/ai-chip-design-startup-edgecortix-brings-total-funding-dasgupta

Dear Friends, every month we publish a small report that collects all the latest information from the FPGA world. Today we present you the report for January 2020. We collected for you more than 70 news about FPGA!!! Download a PDF of the report http://gate-array.com/reports/Report_2020-01-gate-array.com_digest.pdf

>>At Intel, we believe that the best approach to creating DSAs ( domain specific architectures) in the data center – the way that Microsoft has implemented its cloud-based, deep-learning platform for real-time AI inference called Project Brainwave – is to use overlays. Microsoft’s Project Brainwave employs a soft Neural Processing Unit (NPU) implemented with a high-performance Intel® At Intel, we believe that the best approach to creating DSAs in the data center – the way that Microsoft has implemented its cloud-based, deep-learning platform for real-time AI inference called Project Brainwave – is to use overlays. Microsoft’s Project Brainwave employs a soft Neural Processing Unit (NPU) implemented with a high-performance Intel® FPGA to accelerate deep neural network (DNN) inferencing. This NPU DSA has multiple applications in computer vision and natural language processing. to accelerate deep neural network (DNN) inferencing. This NPU DSA has multiple applications in computer vision and natural language processing.

The toolkit speeds up inference on a broad range of Intel hardware: Intel Xeon Scalable and Core CPUs for general-purpose compute, Intel Movidius VPUs for dedicated media and vision applications, and FPGAs for flexible programming logic and scale.

https://www.intel.ai/open-vino-low-precision-pipeline/#gs.vpoihp

https://www.coursera.org/learn/comparch/

For all those interested in Computer Architectures - have a look at this course from Princeton.

Some of the covered topics:
Superscalar
Out-of-Order execution
Branch Prediction
Cache coherency
Vector processors
GPUs
Multiprocessor interconnect

The chapter from the upcoming Vivienne Sze book " Efficient Processing of Deep Neural Networks" http://eyeriss.mit.edu/2020_efficient_dnn_excerpt.pdf

* Processing Near Memory
* Processing in memory
* Processing in the Optical Domain
* Processing in Sensor

AI on steroids

Regarding hardware, Hinton went into an extended explanation of the technical aspects that constrain today's neural networks. The weights of a neural network, for example, have to be used hundreds of times, he pointed out, making frequent, temporary updates to the weights. He said the fact graphics processing units (GPUs) have limited memory for weights and have to constantly store and retrieve them in external DRAM is a limiting factor. 
Much larger on-chip memory capacity "will help with things like Transformer, for soft attention," said Hinton, referring to the wildly popular autoregressive neural network developed at Google in 2017. Transformers, which use "key/value" pairs to store and retrieve from memory, could be much larger with a chip that has substantial embedded memory.

Zdnet

NXP Announces Lead Partnership for Arm Ethos-U55 Neural Processing Unit for Machine Learning
https://media.nxp.com/news-releases/news-release-details/nxp-announces-lead-partnership-arm-ethos-u55-neural-processing/

The Ethos-U55 is specifically designed to accelerate ML inference in area-constrained embedded and IoT devices. Its advanced compression techniques save power and reduce ML model sizes significantly to enable execution of neural networks that previously only ran on larger systems. In addition, a unified toolchain with Cortex-M gives developers a simplified, seamless path to develop ML applications within the familiar Cortex-M development environment. The end-to-end enablement, from training to run-time inference deployment for Ethos-U55, will be accessible through NXP’s eIQ machine learning development environment.

Graphcore has now raised over $450 million and says that it has some $300 million in cash reserves — an important detail considering the doldrums that have plagued the chipmaking market in the last few months, and could become exacerbated now with the slowdown in production due to the coronavirus outbreak.
The funding is an extension of its Series D, it said, and brings the total valuation of the company to $1.95 billion.

The Linley Spring Processor Conference will be held on April 7 - 8, 2020 at the Hyatt Regency Hotel, Santa Clara, California. This two-day conference features in-depth technical presentations addressing processors and IP cores for AI applications, embedded, data center, automotive, and communications. This unique forum focuses on the processors and IP cores used in deep learning, embedded, communications, automotive, IoT, and server designs.

https://www.linleygroup.com/events/event.php?num=48

Participants :
Intel, ARM, SiFive,CEVA, Groq,Cerebras Systems, Mellanox, Cadence

Here we demonstrate that an image sensor can itself constitute an ANN that can simultaneously sense and process optical images without latency. Our device is based on a reconfgurable two-dimensional (2D) semiconductor photodiode array, and the synaptic weights of the network are stored in a continuously tunable photoresponsivity matrix. We demonstrate both supervised and unsupervised learning and train the sensor to classify and encode images that are optically projected onto the chip with a throughput of 20 million bins per second.